1. Field of the Invention
The present invention relates to a data output controller of a high frequency memory device, and more particularly to a controller and a method for controlling a data output of a high-speed memory device by using CAS latency.
2. Description of the Prior Art
Generally, a period of time required for outputting data out of a chip after applying a read command to a memory device is defined in a specification. Typically, such a period of time required for outputting data is represented as CAS latency (CL), which is a number of external clock signals. For instance, if CL is 4, data are outputted after four clocks. The CAS latency is initially determined according to an MRS (mode register set) signal.
That is, since data are outputted from a memory device in accordance with a time defined in the specification, the CAS latency may increase as frequency of the memory device becomes increased. For instance, if the frequency of the memory device increases by two times during a predetermined period of data output time, the CAS latency may increase from 4 to 8. However, currently used high-speed memory devices cannot continuously increase the CAS latency according to an increase of the frequency thereof.
This is because the high-speed memory devices equipped with a conventional CAS latency technique may restrict an operation of an internal counter, which controls the data output time according to the CAS latency. For example, if the CAS latency is 12 and a period of time for an external clock signal tCK is 1 ns, DLL CLK is generally advanced by 3.5 ns and a time required for analyzing a read command is 2.5 ns. In addition, if a period of time from the read command to the data output is 12 ns, a time assigned to an internal counter is 6 ns (12 ns−3.5 ns−2.5 ns=6 ns). Herein, the internal counter generates 11 counter signals in order to synchronize the data output time with the CAS latency of 12. Accordingly, if at least 600 ps of time is required for one counter action of the internal counter, a time for the internal counter is represented as 11×6.6=6.6 ns, which exceeds the time (6 ns) assigned to the internal counter. Therefore, it is difficult to precisely control the data output time.